/* SPDX-License-Identifier: GPL-2.0 */
/*
 * Copyright (c) 2021-2022, Pensando Systems Inc.
 */

#ifndef __ASIC_REGS_CAPRI_H__
#define __ASIC_REGS_CAPRI_H__

#ifdef __cplusplus
extern "C" {
#if 0
} /* close to calm emacs autoindent */
#endif
#endif

#define ASIC_(REG)      CAP_ ##REG
#define PXB_(REG) \
    (CAP_ADDR_BASE_PXB_PXB_OFFSET + CAP_PXB_CSR_ ##REG## _BYTE_ADDRESS)
#define PXC_(REG, pn) \
    (CAP_ADDR_BASE_PP_PP_OFFSET + \
     ((pn) * CAP_PXC_CSR_BYTE_SIZE) + \
     CAP_PP_CSR_PORT_C_ ##REG## _BYTE_ADDRESS)

/* cap_top_csr_defines.h */
#define CAP_ADDR_BASE_INTR_INTR_OFFSET 0x6000000
#define CAP_ADDR_BASE_PP_PP_OFFSET 0x7000000
#define CAP_ADDR_BASE_PXB_PXB_OFFSET 0x7100000

/* cap_pxb_c_hdr.h */
#define CAP_PXB_CSR_DHS_ITR_PCIHDRT_BYTE_ADDRESS 0x8000
#define CAP_PXB_CSR_DHS_TGT_NOTIFY_BYTE_ADDRESS 0x9a000
#define CAP_PXB_CSR_DHS_TGT_PMT_BYTE_ADDRESS 0x18000
#define CAP_PXB_CSR_DHS_TGT_PMR_BYTE_ADDRESS 0x20000
#define CAP_PXB_CSR_DHS_TGT_PRT_BYTE_ADDRESS 0x30000
#define CAP_PXB_CSR_DHS_TGT_AXIMST0_BYTE_ADDRESS 0x62000
#define CAP_PXB_CSR_DHS_TGT_AXIMST1_BYTE_ADDRESS 0x63000
#define CAP_PXB_CSR_DHS_TGT_IND_RSP_ENTRY_BYTE_ADDRESS 0x9a020
#define CAP_PXB_CSR_CFG_TGT_REQ_NOTIFY_INT_BYTE_ADDRESS 0x9a120
#define CAP_PXB_CSR_CFG_TGT_REQ_NOTIFY_RING_SIZE_BYTE_ADDRESS 0x9a130
#define CAP_PXB_CSR_CFG_TGT_REQ_INDIRECT_INT_BYTE_ADDRESS 0x9a140
#define CAP_PXB_CSR_CFG_TGT_NOTIFY_EN_BYTE_ADDRESS 0x9a184
#define CAP_PXB_CSR_CFG_TGT_PMT_GRST_BYTE_ADDRESS 0x9a204
#define CAP_PXB_CSR_STA_TGT_IND_INFO_BYTE_ADDRESS 0x9a320
#define CAP_PXB_CSR_DHS_ITR_PCIHDRT_ENTRIES 0x800
#define CAP_PXB_CSR_DHS_ITR_PCIHDRT_ENTRY_BYTE_SIZE 0x10
#define CAP_PXB_CSR_DHS_TGT_PMT_ENTRY_ARRAY_ELEMENT_SIZE 0x1
#define CAP_PXB_CSR_DHS_TGT_PMR_ENTRY_BYTE_SIZE 0x10
#define CAP_PXB_CSR_DHS_TGT_PRT_ENTRY_BYTE_SIZE 0x10

/* cap_pp_c_hdr.h */
#define CAP_PXC_CSR_BYTE_SIZE 0x2000
#define CAP_PP_CSR_PORT_C_DHS_C_MAC_APB_ENTRY_BYTE_ADDRESS 0x10000

/* cap_intr_c_hdr.h */
#define CAP_INTR_CSR_DHS_INTR_ASSERT_ENTRY_ARRAY_COUNT 0x1000
#define CAP_INTR_CSR_DHS_INTR_MSIXCFG_BYTE_OFFSET 0x10000
#define CAP_INTR_CSR_DHS_INTR_FWCFG_BYTE_OFFSET 0x20000
#define CAP_INTR_CSR_DHS_INTR_DRVCFG_BYTE_OFFSET 0x40000
#define CAP_INTR_CSR_DHS_INTR_ASSERT_BYTE_OFFSET 0x68000
#define CAP_INTR_CSR_DHS_INTR_STATE_BYTE_OFFSET 0x70000

#ifdef __cplusplus
}
#endif

#endif /* __ASIC_REGS_CAPRI_H__ */
